1. Field of the Invention
The present invention relates to a high voltage generating circuit for a semiconductor memory circuit, and more particularly, to a high voltage generating circuit which reduces power consumption due to unnecessary operations.
2. Discussion of the Related Art
Generally, in programing and erasing a flash cell in a flash memory, a charge pump circuit for generating a high voltage is required.
A conventional high voltage generating circuit will be described with reference to the accompanying drawing.
FIG. 1 is a circuit diagram illustrating a conventional high voltage generating circuit.
As shown in FIG. 1, the conventional high voltage generating circuit includes a plurality of charge pumps 100, an output voltage sensor 200, a reference voltage generator 300, a voltage comparator 400, and a clock controller 500.
In the charge pumps 100, there is provided a voltage supplied from a power source voltage terminal Vcc through an NMOS transistor 11. The power source voltage Vcc is in common applied to a gate and a drain of the NMOS transistor 11. A source of the NMOS transistor 11 serves as an output terminal.
Each of the charge pumps 100 includes first and second capacitors 13 and 15 having first and second pump control signals 17 and 18 of different phases as input signals, respectively, and first and second NMOS transistors 14 and 16 connected in series, of which gates are respectively connected to the first and second capacitors 13 and 15, drains and gates are in common connected to the source of the NMOS transistor 11, and the drains serve as respective output terminals.
In the aforementioned charge pump 100, the voltage supplied from the power source voltage terminal Vcc through the NMOS transistor 11 is precharged at Vcc-Vt in the drain of the first NMOS transistor 14. At this time, an input value of the first capacitor 13 is "0".
In view of the fact that there exists voltage difference between both ends of the first capacitor 13, when the first pump control signal 17 has the power source voltage Vcc, the drain of the first NMOS transistor 14 ascends by 2Vcc-Vt and the drain of the second NMOS transistor 16 is precharged at 2(Vcc-Vt).
At this time, the second pump control signal 18 of the second capacitor 15 becomes 0V and the voltage difference between both ends of the second capacitor 15 becomes 2(Vcc-Vt).
Meanwhile, the charge pumps 100 are connected in series to gradually ascend an output voltage 19 by means of the first and second pump control signals 17 and 18.
The output voltage sensor 200 includes first and second resistors 201 and 202 connected in series between the output voltage terminal 19 and a ground voltage terminal Vss, a dynamic resistor circuit 250 connected with the first resistor 201 in parallel, having two dynamic resistors 205 and 206, and first and second EEPROM fuse circuits 210 and 220.
The dynamic resistor circuit 250 includes first and second transistors 205 and 206 and first and second resistors 203 and 204 connected in series between the output voltage terminal 19 and an output node 207 which is interposed between the first and second resistors 201 and 202.
The gates of the first and second transistors 205 and 206 are respectively connected to output terminals 230 and 240 of the first and second EEPROM fuse circuits 210 and 220.
The first and second EEPROM fuse circuits 210 and 220 respectively include first and second depletion transistors 211 and 221 with the drain connected to the ground voltage and the gate connected to the source, floating gate field effect transistors 212 and 222 with the channels connected between the source of the depletion transistors 211 and 221 and the ground voltage and the control gates connected to reset signals 252 and 254, and first and second inverters 213 and 223 for inverting the outputs of the output nodes interposed between the source of the depletion transistors 211 and 221 and the drains of the floating gate field effect transistors 212 and 22 to provide the gates of the transistors 205 and 206 of the dynamic resistor circuit 250.
The floating gate field effect transistors 212 and 222 serve as an EEPROM fuse cell that is erased or programmed according to cell state control signals 251 and 253 applied to the drain thereof.
The reference voltage generator 300 includes first and second depletion transistors 302 and 305 connected in series between the source voltage terminal and the ground voltage terminal, first and second NMOS transistors 303 and 304 connected in series between the first and second depletion transistors 302 and 305, and an inverter 301 for inverting a write enable signal WE to in common provide the gates of the first and second NMOS transistors 303 and 304 with the inverted signal.
The reference voltage is output through an output node 310 from a contact point between the first and second NMOS transistors 303 and 304.
The voltage comparator 400, which serves as a typical differential amplifier, includes two PMOS transistors 403 and 404 and three NMOS transistors 401, 402 and 405. The gate of the NMOS transistor 405 connected to an inverter 406 which inverts the write enable signal WE. The output of the voltage comparator 400 passes through three inverters 407, 408 and 409.
The voltage comparator 400 compares the reference voltage output through the node 310 with a voltage output through a node 260 and varies input values of the inverter 407.
The clock controller 500 includes first and second NOR gates 501 and 502, a first inverter 503, and second and third inverters 504 and 505. A clock pulse signal OP, a write enable signal WE, and the output signals of the voltage comparator 400 are respectively input to the first and second NOR gates 501 and 502. The first inverter 503 inverts an output signal of the first NOR gate 501 and outputs a first pump control signal 17. The second and third inverters 504 and 505 delay an output signal of the second NOR gate 502 and output a second pump control signal 18.
The clock controller 500 is enabled when the write enable signal WE is low. The clock controller 500 generates the first and second pump control signals 17 and 18 of different phases through the inverters 503, 504 and 505 when the node 410 is low by the clock pulse signal OP.
In the conventional high voltage generating circuit, the output voltage 19 ascends by means of the voltage pumps 100 and the size of a desired output voltage is determined by the output voltage sensor 200.
If the output voltage 19 is lower than a given voltage, the voltage of the node 310 becomes higher than the voltage of the node 260, so that the input of the inverter 407 becomes high and the voltage of the node 410 becomes low. As a result, since the outputs of the NOR gates 501 and 502 are determined by the clock pulse signal OP regardless of the node 410, the input signals of the charge pumps 100, i.e., the first and second pump control signals 17 and 18 have different phases to allow the charge pumps 100 to perform normal operation.
While, if the output voltage 19 is higher than a given voltage, the voltage of the node 310 becomes lower than the voltage of the node 260, so that the input of the inverter 407 becomes low and the voltage of the node 410 becomes high. As a result, since the outputs of the NOR gates 501 and 502 become low regardless of the clock pulse signal OP, the input signals of the charge pumps 100, i.e., the first and second pump control signals 17 and 18 become high and low, respectively, so as not to operate the charge pumps 100.
The aforementioned conventional high voltage generating circuit has several problems.
Since the charge pumps are not operated if the output voltage is lower than the given voltage, current is supplied from the output voltage during programming, thereby rapidly lowering the output voltage. In other words, increasing voltage ripple in the course of reducing the output voltage causes poor program performance.